1. Field of the Disclosure
The present disclosure relates to decoding methods, and particularly to a decoding method to decode a digital signal.
2. Description of Related Art
Referring to FIG. 3, two coordinate digital signals to be decoded by a typical digital signal decoding method is shown. According to this typical digital signal decoding method, after a semi-period (such as 0.56 ms in one example) low voltage, the digital signal reaches a rising edge, a voltage of a time point (such as 0.84 ms in one example) which is between a semi-period and a period after the rising edge is collected. If the collected voltage is at the high level (shown at a broken line of the upper schematic view), the digital signal is decoded as logical “1.” If the collected voltage is at the low level (shown at a broken line of the lower schematic view), the digital signal is decoded as logical “0.” However, if the frequency of the digital signal is unstable, the decoded logical codes maybe not correct.
What is needed is to provide a digital signal decoding method which can correctly decode a digital signal even the frequency of the digital signal is unstable.